The invention relates to a method of enhancing the noise immunity of a phase-locked loop used in the field of television signal processing, especially when locking onto the frequency of synchronization signals. The invention relates also to a device comprising a phase-locked loop and implementing the said method.
The invention is intended particularly for phase-locked loops produced as integrated circuits, particularly in MOS technology, more particularly CMOS technology.
A functional diagram of a conventional phase-locked loop is represented in FIG. 1. According to this specific example of the prior art, the PLL receives a reference signal consisting of synchronization pulses derived by a synchronization extractor 1 from the composite video baseband signal, CVBS.
A phase comparator 2 receives the synchronization thus extracted on one of its inputs. A filter 3, as well as a voltage-controlled oscillator (or VCO) 4 are connected in series with the phase comparator 2. The output of the VCO is looped back onto another input of the phase comparator 2. The return loop includes a frequency divider by N, referenced 5.
When the device is locked, the input signals of the phase comparator 2 are in phase, the voltage on the filter 3 does not vary and the output frequency of the VCO is constant. This frequency is equal to N times the frequency of the synchronization.
In the event of a jump in the phase of the synchronization signal coming from the extractor 1 (reference signal), the said synchronization signal and the looped-back signal are no longer in phase. The comparator then causes the voltage on the filter 3 to vary, and consequently the voltage at the input of the VCO 4. The output frequency of the latter then varies in such a way as to put the two input signals of the phase comparator 2 back in phase.
FIG. 2a shows an example of a CVBS signal, as well as two defects 6 and 7 possibly leading to erroneous synchronization pulses being obtained. Such a noisy CVBS signal is encountered in practice, for example at the output of a video recorder.
FIG. 2b represents the signal derived by the synchronization extractor 1 from the CVBS signal represented by FIG. 2a. The defect 6 creates a stray pulse 6a, while the defect 7 causes a pulse to be absent. In both cases, there is unlocking of the PLL loop.
The output frequency of the PLL loop is thus prone to variations. The latter can be troublesome particularly in the following three cases:
When the gain of the VCO 4 is high, variations in the output frequency are large even for small variations in voltage at the input of the said VCO. PA1 When the phase comparator 3 includes a phase-frequency detector, (PFD), possessing logic outputs as described below, a small phase jump at the input can cause it to trip over. There is no gradation between the high state and the low state of the. PFD outputs. As in the case of high gain of the VCO 4, this can cause rapid variations ("jitter") of the output frequency. PA1 When the output frequency is driving digital circuits, even slight variations in the said frequency can occasion malfunctioning.
Such defects are encountered particularly in integrated circuits, for example circuits of the CMOS type.
The purpose of the invention is to avoid the unlocking of a phase-locked loop due to a CVBS signal of mediocre quality. In consequence, one object of the invention is to enhance the noise immunity of a phase-locked loop and to minimize the rapid variations or "jitter" of the output frequency of the phase-locked loop.
The subject of the invention is a method of enhancing the noise immunity of a phase-locked loop, the said phase-locked loop comprising a comparator and means for inhibiting the action of the comparator on the said phase-locked loop, the said method being characterized in that the said inhibition is lifted in the course of a main time window resulting from the intersection of a first time window derived from the input signal of the phase-locked loop and of a second time window derived from the loop return signal.
In what follows, the term "reference signal" refers to the signal to the frequency of which it is desired to lock the PLL loop. It relates therefore to the signal sent to the comparator of the said loop.
The term "input signal" refers to the signal serving to derive the said reference signal.
According to one particular embodiment, the said reference signal comprises strobes derived, by reshaping, from pulses extracted from the said input signal.
According to one particular embodiment, the said first window is triggered by a pulse of the input signal of the phase-locked loop.
According to one particular embodiment, the first window is for the purpose of enabling the action of the comparator in the presence of a pulse in the input signal.
According to one particular embodiment, the comparator receives a reference signal comprising strobes derived from pulses extracted from the input signal.
According to one particular embodiment, the said window is physically represented by strobes derived from pulses of the input signal, the strobes of the analog window overlapping, in terms of time, the active edge of the corresponding strobes of the reference signal sent to the comparator.
According to one particular embodiment, the signal corresponding to the first window includes a strobe when a pulse of the input signal exceeds and first voltage threshold.
According to one particular embodiment, the reference signal includes a strobe when a pulse of the input signal exceeds a second voltage threshold situated between the first voltage threshold and the peak pulse voltage.
According to one particular embodiment, the said second window enables the action of the comparator only around the active edge of the loop return signal.
According to one particular embodiment, the phase-locked loop comprises a frequency divider in its return loop, the said divider comprising an N-state counter counting the output pulses of the phase-locked loop, the said divider generating the loop return signal sent to the comparator.
According to one particular embodiment, the said second window enables the action of the comparator only during the x states preceding and the y states following the transition of the divider which defines the active edge of the loop return signal.
According to one particular embodiment, the inhibiting action of the signal corresponding to the second window is implemented only when the phase-locked loop is locked.
According to one particular embodiment, the locking state is defined by a boolean variable (MUTE), set to the true state when, for n successive pulses extracted from the input signal, the corresponding active edges of the reference signal lie within the second window.
According to one particular embodiment, the said boolean variable (MUTE) is set to the false state when, for n successive pulses extracted from the input signal, the corresponding active edges of the reference signal lie within the second window.
According to one particular embodiment, the signal corresponding to the main time window results from a logic "AND" between the signal corresponding to the first window and the signal corresponding to the second window.
A further subject of the invention is a device including a phase-locked loop and implementing the method in accordance with the invention, characterized in that the said device comprises means for creating the main time window during which the comparator can act on the output frequency of the said phase-locked loop, the said comparator being a phase and/or frequency comparator the outputs of which control the transistors of a charge-pump circuit charging a loop filter, the outputs of the comparator being inactivated outside the said time window.
According to one particular embodiment of the device in accordance with the invention, the means of deriving the main time window comprise means of deriving a first time window includings slew-rate-controlled amplifier, the output of which is connected to a peak detector feeding a resistor bridge one connection of which supplies the desired percentage of the said peak value to the negative input of a comparator, the positive input of the said comparator being connected to the output of an amplifier, the output of the said comparator supplying the signal representing the said first window.